AMD Ryzen ThreadRipper PRO 3955WX - 3.9 GHz - 16-core - 32 threads - 64 MB cache - Socket sWRX8 - Box

AMD Ryzen Threadripper PRO processor is the first and only professional workstation-caliber CPU to exploit a 7 nm silicon manufacturing process, allowing engineers to double the density and fueling the transistor budget needed to substantially drive-up core throughput. With the unveiling of the first generation of "Zen" CPU technology, AMD disrupted the status quo with a microarchitecture completely rebuilt from the ground up and optimized for modern single and multi-threaded workloads. With the Threadripper PRO processor's "Zen 2" microarchitecture, improvements are many, but two carry most of the weight, especially where high demand professional computing is concerned: up to 15% faster instructions per cycle (IPC), and an impressive quadrupling of the peak floating point throughput rate. The former comes primarily by the way of improved branch prediction and pre-fetching, supported by much deeper and broader allocation of cache, while the latter is the result achieved by both doubling the width of the FPU data path and doubling density. Supporting the increased compute throughput, architects doubled load-store bandwidth and dialed up dispatch and retire bandwidth to minimize the chances the higher throughput ALUs would be starved of data.

AMD Ryzen Threadripper PRO processor is the first and only professional workstation-caliber CPU to exploit a 7 nm silicon manufacturing process, allowing engineers to double the density and fueling the transistor budget needed to substantially drive-up core throughput. With the unveiling of the first generation of "Zen" CPU technology, AMD disrupted the status quo with a microarchitecture completely rebuilt from the ground up and optimized for modern single and multi-threaded workloads. With the Threadripper PRO processor's "Zen 2" microarchitecture, improvements are many, but two carry most of the weight, especially where high demand professional computing is concerned: up to 15% faster instructions per cycle (IPC), and an impressive quadrupling of the peak floating point throughput rate. The former comes primarily by the way of improved branch prediction and pre-fetching, supported by much deeper and broader allocation of cache, while the latter is the result achieved by both doubling the width of the FPU data path and doubling density. Supporting the increased compute throughput, architects doubled load-store bandwidth and dialed up dispatch and retire bandwidth to minimize the chances the higher throughput ALUs would be starved of data.